This circuit can switch two or more devices on and off in response to a
series of rapid handclaps. The claps are picked up by an electret
microphone and amplified by a 741 op amp (IC1). IC1 is configured as an
inverting amplifier, with its gain and hence the sensitivity of the
circuit adjustable via trimpot VR1. Its output is then fed into a
pulse-shaping stage based on a 555 timer (IC2). The 555 is configured as
a monostable multivibrator, with its trigger input (pin 2) normally
biased to about 0.4VCC by the 150kW and 100kW resistors. When a loud
enough sound is detected, pin 2 will be pulled below 1/3VCC, triggering
the monostable. The output (pin 3) will immediately swing high, causing
transistor Q1 to conduct.
The result is a 250ms low-going pulse at the collector of Q1. The output from the pulse-shaper stage is fed into a missing-pulse detector based on a second 555 timer (IC3), which is also configured as a monostable multivibrator. However, this monostable circuit differs from the first because it includes a "retrigger" function. Retriggering is made possible by transistor Q2, which acts to rapidly discharge the 10mF timing capacitor should a pulse arrive when the timer is already running. This means that once triggered, IC3’s output will remain high as long as additional trigger pulses are received within its set timing period. Pulses from Q1’s collector are also applied to the clock (CP0) input of a 4017 decade counter (IC4).
The result is a 250ms low-going pulse at the collector of Q1. The output from the pulse-shaper stage is fed into a missing-pulse detector based on a second 555 timer (IC3), which is also configured as a monostable multivibrator. However, this monostable circuit differs from the first because it includes a "retrigger" function. Retriggering is made possible by transistor Q2, which acts to rapidly discharge the 10mF timing capacitor should a pulse arrive when the timer is already running. This means that once triggered, IC3’s output will remain high as long as additional trigger pulses are received within its set timing period. Pulses from Q1’s collector are also applied to the clock (CP0) input of a 4017 decade counter (IC4).
In the initial state, output 0 (pin 3) of the counter is high,
illuminating LED1. The first pulse advances the count and lights LED2,
indicating that the circuit is active and ready to receive a handclap
"command". Each time another pulse (clap) is received before IC3’s
timing period expires, the process repeats, incrementing the counter by
one. When IC3’s timing period is allowed to expire (ie, no claps have
been detected for 750ms), the output (pin 3) will go low, turning off
transistors Q3 & Q4. The rising voltage on the collector of
transistor Q3 clocks two J-K flipflops (IC5a & IC5b), with the
result at their Q outputs dependent on the state of the O2-O5 counter
outputs. Considering all the possible logic states of a J-K flipflop,
the "commands" will therefore be:
2) - claps: turn Device 1 on
3) - claps: turn Device 1 off
4) - claps: turn Device 2 on
5) - claps: turn Device 2 off
Finally, the rising voltage on the collector of Q4 resets the counter, ready for the next clap sequence. Note the addition of a 10nF capacitor between the reset input (pin 15) and ground, which in conjunction with the 10kW resistor adds a short delay to the reset signal. This ensures that the counter is not reset until after the J-K flipflops have been clocked. If desired, the circuit could easily be expanded by adding more flip-flops and counters.
2) - claps: turn Device 1 on
3) - claps: turn Device 1 off
4) - claps: turn Device 2 on
5) - claps: turn Device 2 off
Finally, the rising voltage on the collector of Q4 resets the counter, ready for the next clap sequence. Note the addition of a 10nF capacitor between the reset input (pin 15) and ground, which in conjunction with the 10kW resistor adds a short delay to the reset signal. This ensures that the counter is not reset until after the J-K flipflops have been clocked. If desired, the circuit could easily be expanded by adding more flip-flops and counters.
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